Dwscription of the Related Art
The invention relates to an A/D conversion device intended, to convert an analog input voltage into a digital output signal encoded in N bits OUT(0:N-1), in which each bit OUT(i), for i=0 to N-1, must successively assume active and inactive states when the value of the input voltage exceeds (2m+1) and (2m+2) times, respectively, a predetermined value Vi which is associated with said bit OUT(i) wherein m may vary between 0 and 2.sup.(N-1-i) -1, said device comprising:
a resistance ladder arranged in series between two power supply terminals and intended to generate a series of reference voltages, PA1 a series of comparators, each of which having intended to effect a comparison between the input voltage and a reference voltage, PA1 a first decoder intended to generate, on the basis of the results of said comparisons, the K+1 least significant bits OUT(0:K) of the output signal, PA1 a second decoder intended to generate, on the basis of the results of said comparisons, signals which are representative of the transitions to which the N-K-1 most significant bits OUT(i+1) of the output signal are to be submitted, for i=K to N-2, and PA1 an encoder intended to produce each of said most significant bits OUT(i+1) of the output signal, notably on the basis of the signals generated by the first and second decoders.
Such an A/D conversion device is known from U.S. Pat. No. 4,939,517. In this device, the first decoder generates the least significant bits of the digital output signal in a precise manner, while the second decoder generates signals which constitute approximations of the most significant bits of the digital output signal. The encoder receives these signals, as well as the least significant bits delivered by the first decoder. It also receives, from a synchronizing control circuit, signals intended to signal the input voltage variation ranges in which the most significant bits are to be submitted to transitions. To ensure a synchronization of said transitions with the transitions of the least significant bits, the encoder substitutes a logic combination between said signal and at least one of the least significant bits for each output signal of the second decoder, the resultant signal of this logic combination then constituting one of the most significant bits of the digital output signal.
The conversion technique described above is only efficient if the number of most significant bits is reduced, and is limited in frequency. Indeed, the width of the input voltage variation range during which the bit OUT(K) having the highest weight among the least significant bits has a stable state is 2.sup.i smaller than that during which a bit OUT(K+i) of having the weight K+i has a stable state. The larger i is, the more difficult it is for the encoder to synchronize the transitions of the most significant bits with the correct transition of the least significant bits, because this transition becomes more difficult to identify. This leads to a limitation in the dynamic performance of the converter because the, difficulties of synchronization described above become greater as the frequency by which the input voltage varies increases. Delays in the propagation of signals within the device may lead to, for example, a situation where transitions of the least significant bits, which are to serve as references for synchronization, occur outside intervals where the necessary transitions of a most significant bit are signaled by the synchronizing control circuit. Thus appears a critical frequency intrinsic within the circuit: when the frequency of the input voltage exceeds this critical frequency, the precision of the A/D conversion brutally declines.